1. Field of the Invention
The present invention relates to a method for forming a contact for an electrode or a wiring containing aluminum or mainly aluminum.
2. Description of the Related Art
A thin film transistor (TFT) produced in a producing process as shown in FIGS. 2A to 2D has been known. The TFT as shown in FIGS. 2A to 2D is formed on a glass substrate and has a low OFF current characteristic. The low OFF current is an important factor in a case wherein the TFT is utilized for an active matrix type liquid crystal display device or other thin film integrated circuit.
The TFT of FIGS. 2A to 2D has an electrically buffer region which is offset gate regions formed between a channel forming region and source/drain regions, to improve an OFF current characteristic. The structure of FIGS. 2A to 2E is disclosed in Japanese Patent Application Open No. 4-360580, for example.
A process for producing the TFT of FIG. 2D is described below. A glass substrate 201 is prepared and then a silicon oxide film 202 is formed on a surface of the substrate 201 by sputtering or plasma chemical vapor deposition (plasma CVD). The silicon oxide film 202 is a base film for preventing diffusion of an impurity and the like from the glass substrate 201. An amorphous silicon film is formed by plasma CVD or low pressure thermal CVD. If necessary, heating treatment or laser light irradiation is performed to crystallize the amorphous silicon film. If a low characteristic is permitted, it is not necessary to crystallize the amorphous silicon film.
The amorphous silicon film is patterned to form an active layer 203 of a TFT. Then, a silicon oxide film 204 used as a gate insulating film is formed by plasma CVD or sputtering. Also, an aluminum film is formed and then patterned to form a gate electrode 205. (FIG. 2A)
Using an electrolytic solution, anodization is performed with the gate electrode 205 as an anode, to form an anodic oxide film 206 around the gate electrode 205. In the TFT of FIG. 2D, a method for forming the anodic oxide film 206 is an important point. (FIG. 2B)
In FIG. 2C, an impurity ion (phosphorus (P) ion) used to form source and drain regions is implanted by ion implantation or plasma doping. In this process, since the gate electrode 205 and the anodic oxide film formed around the gate electrode 205 are used as masks, the impurity ion is not implanted into a region under the masks. Thus, a source region 207 and a drain region 210 can be formed. A region 208 into which the impurity ion is not implanted can be formed as an offset gate region. A region 209 can be formed as a channel forming region.
Since this impurity ion implantation process of FIG. 2C can be performed in a self-alignment, a complicated process such as a mask alignment is not required, extremely high productivity can be obtained and dispersion elements having no dispersion in characteristic can be obtained.
After the ion implantation process of FIG. 2C, a silicon oxide film 211 is formed as an interlayer insulating film. Also, contact holes are formed and then a source electrode 212 and a drain electrode 213 are formed. At the same time, a lead electrode 214 from the gate electrode 205 is formed. In FIG. 2D, although the source and drain regions 212 and 213 and the lead electrode 214 from the gate electrode 205 are shown each other in the same cross section, the lead electrode 214 from the gate electrode 205 is formed in a front side or an opposite side of the figure, actually.
The TFT produced by the process of FIGS. 2A to 2D has good characteristic and a superior offset gate region. Also, in an active matrix type liquid crystal display device having a large display area and other large scale integrated circuit, it is extremely effective to use aluminum in a gate electrode since a wiring resistance is decreased. In particular, in a case of an insulated gate type field effect transistor which is voltage-controlled, this is very important. In the structure of FIG. 2D, since a gate electrode and a wiring are covered with a fine anodic oxide film having a high withstanding voltage, the problems with respect to a leak or an interaction to various wirings formed on an interlayer insulating film can be solved.
Although the TFT of FIG. 2D is utilized, an extremely difficult state occurs in the process of FIG. 2D. In the process of FIG. 2D, it is required that contact holes for source and drain electrodes 212 and 213 and a contact hole for the lead electrode 214 from the gate electrode 205 are formed at the same time.
Since a removing film is the silicon oxide films 204 and 211, the contact holes for the source and drain regions 212 and 213 are formed by wet etching using a hydrofluoric acid system etchant, for example, buffer hydrofluoric acid (BHF). With respect to the buffer hydrofluoric acid, an etching rate to silicon is markedly smaller than that to silicon oxide. Thus, etching can be completed at a state wherein etching reaches the active layer 203. That is, the active layer 203 can be used as an etching stopper.
However, when the contact hole for the lead electrode 214 is formed, it is necessary to etch the silicon oxide film 211 and the aluminum oxide layer (containing mainly Al.sub.2 O.sub.3) 206 formed by anodization. When this etching is performed using the buffer hydrofluoric acid, It has confirmed that it is difficult to complete etching at the time when the aluminum oxide layer 206 is etched completely. This is a cause that etching of the aluminum oxide layer 206 by a hydrofluoric acid system etchant does not progress uniformly, but it progresses while crumbling easily. This is because, etching of aluminum does not progress after etching of the aluminum oxide layer 206, but etching to the gate electrode 205 of aluminum progresses by a permeated etchant at the same time during etching of the aluminum oxide layer 206. Also, this is a common problem in a case wherein a hydrofluoric acid system etchant is used.
A state that the oxide layer 206 is etched by the hydrofluoric acid system etchant is shown in FIGS. 3A and 3B. In FIG. 3A, the silicon oxide film 211 is etched by the hydrofluoric acid system etchant (for example, buffer hydrofluoric acid). Then, the aluminum oxide layer 206 is etched. In this state, the gate electrode 205 made of aluminum is also etched while the oxide layer 206 is etched.
A thickness of the oxide layer 206 is about 2000 .ANG., and a thickness of the gate electrode 205 is about 4000 to 7000 .ANG.. Generally, an etching speed (etching rate) of the aluminum oxide layer 206 is several 10% larger than that of aluminum. Also, the oxide layer 206 is not etched uniformly and finely and but it is removed by crumbling. When the oxide layer 206 is etched completely, overetching as shown in numeral 302 occurs. Thus, the remainders of the oxide layer 206 and the silicon oxide film 211 in an upper portion of an overetched portion 302 may be caved. This can be just understood as the same phenomenon as a process using a lift off method, and is a cause of insufficient operation of a TFT.